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19-2285; Rev 0; 1/02
Quad Differential LVECL-to-LVPECL Translators
General Description
The MAX9420-MAX9423 are extremely fast, low-skew quad LVECL-to-LVPECL translators designed for highspeed signal and clock driver applications. The devices feature ultra-low propagation delay of 336ps and channel-to-channel skew of 17ps. The four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. These devices operate with a negative supply voltage of -2.0V to -3.6V, compatible with LVECL input signals. The positive supply range is 2.375V to 3.6V for differential LVPECL output signals. A variety of input and output terminations are offered for maximum design flexibility. The MAX9420 has open inputs and open-emitter outputs. The MAX9421 has open inputs and 50 series outputs. The MAX9422 has 100 differential input impedance and open-emitter outputs. The MAX9423 has 100 differential input impedance and 50 series outputs. The MAX9420-MAX9423 are specified for operation from -40C to +85C, and are offered in space-saving 32-pin 5mm 5mm TQFP and 32-lead 5mm 5mm QFN packages.
Features
o >500mV Differential Output at 3.0GHz Clock o 336ps (typ) Propagation Delay in Asynchronous Mode o 17ps (typ) Channel-to-Channel Skew o Integrated 50 Outputs (MAX9421/MAX9423) o Integrated 100 Inputs (MAX9422/MAX9423) o Synchronous/Asynchronous Operation
MAX9420-MAX9423
Ordering Information
PART MAX9420EHJ MAX9421EHJ MAX9422EHJ MAX9423EHJ TEMP RANGE PINDATA OUTPUT PACKAGE INPUT Open Open Open Open 100 100 100 100 Open Open 50 50 Open Open 50 50
-40C to +85C 32 TQFP -40C to +85C 32 TQFP -40C to +85C 32 TQFP -40C to +85C 32 TQFP
MAX9420EGJ* -40C to +85C 32 QFN MAX9421EGJ* -40C to +85C 32 QFN MAX9422EGJ* -40C to +85C 32 QFN MAX9423EGJ* -40C to +85C 32 QFN
Applications
Data and Clock Driver and Buffer Central Office Backplane Clock Distribution DSLAM Backplane
*Future product--contact factory for availability.
Pin Configurations
OUT0 GND VCC IN0 IN0 IN1 26 32 VEE SEL SEL CLK CLK EN EN 1 2 3 4 5 6 7 8 9 IN3 10 IN3 11 VCC 12 OUT3 13 OUT3 14 GND 15 IN2 16 IN2 31 30 29 28 27 IN1 25 24 VCC 23 OUT1 22 OUT1 21 GND 20 GND 19 OUT2 18 OUT2 17 VCC
Base Station ATE
TOP VIEW
MAX9420 MAX9421 MAX9422 MAX9423
Functional Diagram appears at end of data sheet.
VEE
TQFP (5mm x 5mm)
Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
OUT0
Quad Differential LVECL-to-LVPECL Translators MAX9420-MAX9423
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.1V VEE to GND............................................................-4.1V to +0.3V Inputs to GND .............................................(VEE - 0.3V) to +0.3V Differential Input Voltage .......................................................3V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA Continuous Power Dissipation (TA = +70C) Single-Layer PC Board 32-Pin 5mm 5mm TQFP (derate 9.5mW/C above +70C) ................................761mW 32-Lead 5mm 5mm QFN (derate 21.3mW/C above +70C) .................................1.7W Junction-to-Ambient Thermal Resistance in Still Air 32-Pin 5mm 5mm TQFP......................................+105C/W 32-Lead 5mm 5mm QFN ......................................+47C/W Junction-to-Ambient Thermal Resistance with 500 LFPM Airflow 32-Pin 5mm 5mm TQFP.........................................+73C/W Junction-to-Case Thermal Resistance 32-Pin 5mm 5mm TQFP.........................................+25C/W 32-Lead 5mm 5mm QFN .........................................+2C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (IN_, IN_) ........................................500V Others.............................................................................1.2kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VEE = -2.0V to -3.6V, VCC = 2.375V to 3.6V, GND = 0, MAX9420/MAX9422 outputs terminated with 50 1% to VCC - 2.0V. Typical values are at VEE = -3.3V, VCC = 3.3V, TA = +25C, VIHD = -0.9V, VILD = -1.7V, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER SYMBOL CONDITIONS MIN VEE + 1.4 VEE VEE -3.0V VEE > -3.0V EN, EN, SEL, SEL , IN_, IN_, CLK, or CLK = VIHD or VILD EN, EN, SEL, SEL, CLK, or CLK = VIHD or VILD 0.2 0.2 -10 -10 86 100 TYP MAX UNITS
LVECL INPUTS (IN_, IN_, CLK, CLK, EN, EN, SEL, SEL) Differential Input High Voltage Differential Input Low Voltage Differential Input Voltage VIHD VILD VID Figure 1 Figure 1 Figure 1 MAX9420/ MAX9421 Input Current IIH, IIL MAX9422/ MAX9423 0 -0.2 3.0 VEE 25 A 25 114 V V V
Differential Input Resistance (IN, IN) LVPECL OUTPUTS (OUT_, OUT_) Differential Output Voltage Output Common-Mode Voltage Internal Current Source Output Impedance
RIN
MAX9422/MAX9423
VOH VOL VOCM ISINK ROUT
Figure 1 Figure 1 MAX9421/MAX9423, Figure 2 MAX9421/MAX9423, Figure 2
600 VCC 1.5 6.5 40 VCC 1.25 8.2 50
660 VCC 1.1 10.0 60
mV V mA
2
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Quad Differential LVECL-to-LVPECL Translators
DC ELECTRICAL CHARACTERISTICS (continued)
(VEE = -2.0V to -3.6V, VCC = 2.375V to 3.6V, GND = 0, MAX9420/MAX9422 outputs terminated with 50 1% to VCC - 2.0V. Typical values are at VEE = -3.3V, VCC = 3.3V, TA = +25C, VIHD = -0.9V, VILD = -1.7V, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER POWER SUPPLY Negative Supply Current Positive Supply Current IEE ICC OUT_, OUT_ open OUT_, OUT_ open MAX9421/MAX9422/ MAX9423 MAX9421/MAX9423 MAX9420/MAX9422 7 153 87 10 -180 105 mA mA SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9420-MAX9423
AC ELECTRICAL CHARACTERISTICS
(VEE = -2.0V to -3.6V, VCC = 2.375V to 3.6V, GND = 0, outputs terminated with 50 1% to VCC - 2.0V. For SEL = high, CLK = high or low, fIN = 2.0GHz. For SEL = low, FIN = 1.5GHz, CLK = 3.0GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.4V to 0, VILD = VEE to -0.2V, VIHD - VILD = 0.2V to the smaller of 3.0V or |VEE|. Typical values are at VEE = -3.3V, VCC = 3.3V, GND = 0, TA = +25C, VIHD = -0.9V, VILD = -1.7V, unless otherwise noted.) (Note 4)
PARAMETER IN-to-OUT Differential CLK-to-OUT Differential IN-to-OUT Channel-to-Channel Skew (Note 5) CLK-to-OUT Channel-toChannel Skew (Note 5) Maximum Clock Frequency Maximum Data Frequency Added Random Jitter (Note 6) SYMBOL CONDITIONS MIN 250 350 TYP 336 506 17 17 3.0 2 0.65 0.53 28 23 80 80 90 120 1.0 1.0 45 ps(P-P) 45 ps ps ps MAX 450 575 60 55 UNITS ps ps ps ps GHz GHz ps(RMS) ps(RMS)
tPLH1, tPHL1 SEL = high, Figure 3 tPLH2, tPHL2 SEL = low, Figure 4 tSKD1 tSKD2 fCLK(MAX) fIN(MAX) tRJ SEL = high SEL = low VOH - VOL 500mV, SEL = low VOH - VOL 400mV, SEL = high SEL = low, fCLK = 3.0GHz, fIN = 1.5GHz SEL = high, fIN = 2GHz SEL = low, fCLK = 3.0GHz, IN_ = 3.0Gbps, 223 - 1 PRBS pattern tDJ SEL = high, IN_ = 3.0Gbps 223 - 1 PRBS pattern Figure 4 Figure 4 Figure 3
Added Deterministic Jitter (Note 6) IN-to-CLK Setup Time CLK-to-IN Hold Time Output Rise Time
tS tH tR
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3
Quad Differential LVECL-to-LVPECL Translators MAX9420-MAX9423
AC ELECTRICAL CHARACTERISTICS (continued)
(VEE = -2.0V to -3.6V, VCC = 2.375V to 3.6V, GND = 0, outputs terminated with 50 1% to VCC - 2.0V. For SEL = high, CLK = high or low, fIN = 2.0GHz. For SEL = low, FIN = 1.5GHz, CLK = 3.0GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.4V to 0, VILD = VEE to -0.2V, VIHD - VILD = 0.2V to the smaller of 3.0V or |VEE|. Typical values are at VEE = -3.3V, VCC = 3.3V, GND = 0, TA = +25C, VIHD = -0.9V, VILD = -1.7V, unless otherwise noted.) (Note 4)
PARAMETER Output Fall Time Propagation Delay Temperature Coefficient SYMBOL tF tPD/ T Figure 3 CONDITIONS MIN TYP 90 0.2 MAX 120 1 UNITS ps ps/C
Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +25C. DC limits are guaranteed by design and characterization over the full operating temperature range. Note 4: Guaranteed by design and characterization. Limits are set to 6 sigma. Note 5: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 6: Device jitter added to the input signal.
Typical Operating Characteristics
(VEE = -3.3V, VCC = 3.3V, GND = 0, MAX9420/MAX9422 outputs terminated with 50 1% to VCC - 2.0V, SEL = high, fCLK = 3.0GHz, fIN = 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = -0.9V, VILD = -1.7V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT (ICC) vs. TEMPERATURE
MAX9420 toc01
SUPPLY CURRENT (IEE) vs. TEMPERATURE
MAX9420 toc02
OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY
MAX9420/MAX9422 SEL = HIGH OUTPUT AMPLITUDE (mV) 800
MAX9420 toc03
100 95 SUPPLY CURRENT (mA) 90 85 80 75 70 -40 -15 10 35 60 MAX9420/MAX9422 SEL = HIGH OUTPUTS NOT TERMINATED
9 MAX9420/MAX9422 SEL = HIGH OUTPUTS NOT TERMINATED
1000
OUTPUT AMPLITUDE (mV)
8
7
600
6
400
5
200
4 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
0 0 500 1000 1500 2000 2500 3000 3500 IN_ FREQUENCY (MHz)
OUTPUT RISE/FALL TIME vs. TEMPERATURE
MAX9420 toc04
IN-TO-OUT PROPAGATION DELAY vs. TEMPERATURE
MAX9420 toc05
CLK-TO-OUT PROPAGATION DELAY vs. TEMPERATURE
MAX9420/MAX9422 SEL = LOW
MAX9420 toc06
100 MAX9420/MAX9422 SEL = HIGH OUTPUT RISE/FALL TIME (ps) 95 tR tF 85
370 360 PROPAGATION DELAY (ps) 350 340 330 tPHL1 320 310 300 tPLH1 MAX9420/MAX9422 SEL = HIGH
600 575 PROPAGATION DELAY (ps) 550 525 500 475 450 425 tPLH2 tPHL2
90
80
75 -40 -15 10 35 60 85 TEMPERATURE (C)
290 -40 -15 10 35 60 85 TEMPERATURE (C)
-40
-15
10
35
60
85
TEMPERATURE (C)
4
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Quad Differential LVECL-to-LVPECL Translators
Pin Description
PIN 1, 8 NAME VEE FUNCTION Negative Supply Voltage. Bypass VEE to GND with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Noninverting Differential Select Input. Setting SEL = high and SEL = low (differential high) enables all four channels to operate asynchronously. Setting SEL = low and SEL = high (differential low) enables all four channels to operate in synchronous mode. Inverting Differential Select Input Inverting Differential Clock Input. A rising edge on CLK (and falling on CLK) transfers data from the inputs to the outputs when SEL = differential low. Noninverting Differential Clock Input Noninverting Differential Output Enable Input. Setting EN = high and EN = low (differential high) enables the outputs. Setting EN = low and EN = high (differential low) drives the output low. Inverting Differential Output Enable Input Noninverting Differential Input 3 Inverting Differential Input 3 Positive Supply Voltage. Bypass VCC to GND with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Inverting Differential Output 3 Noninverting Differential Output 3 Ground Noninverting Differential Input 2 Inverting Differential Input 2 Inverting Differential Output 2 Noninverting Differential Output 2 Noninverting Differential Output 1 Inverting Differential Output 1 Inverting Differential Input 1 Noninverting Differential Input 1 Noninverting Differential Output 0 Inverting Differential Output 0 Inverting Differential Input 0 Noninverting Differential Input 0 Exposed Paddle (MAX942_EGJ only). Connected to VEE internally. See package dimensions.
MAX9420-MAX9423
2 3 4 5 6 7 9 10 11, 17, 24, 30 12 13 14, 20, 21, 27 15 16 18 19 22 23 25 26 28 29 31 32 --
SEL SEL CLK CLK EN EN IN3 IN3 VCC OUT3 OUT3 GND IN2 IN2 OUT2 OUT2 OUT1 OUT1 IN1 IN1 OUT0 OUT0 IN0 IN0 EP
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5
Quad Differential LVECL-to-LVPECL Translators MAX9420-MAX9423
Detailed Description
The MAX9420-MAX9423 are extremely fast, low-skew quad LVECL-to-LVPECL translators designed for highspeed signal and clock driver applications. The devices feature ultra-low propagation delay of 336ps and channel-to-channel skew of 17ps. The four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. These devices operate with a negative supply voltage of -2.0V to -3.6V, compatible with LVECL input signals. The positive supply range is 2.375V to 3.6V for differential LVPECL output signals. A variety of input and output terminations are offered for maximum design flexibility. The MAX9420 has open inputs and open-emitter outputs. The MAX9421 has open inputs and 50 series outputs. The MAX9422 has 100 differential input impedance and open-emitter outputs. The MAX9423 has 100 differential input impedance and 50 series outputs.
Outputs
The MAX9421/MAX9423 have internal 50 series output termination resistors and 8mA internal pulldown current sources. Using integrated resistors reduces external component count. The MAX9420/MAX9422 have open-emitter outputs. An external termination is required. See the Output Termination section.
Enable
Setting EN = high and EN = low enables the device. Setting EN = low and EN = high forces the outputs to a differential low. All changes on CLK, SEL, and IN_ are ignored.
Asynchronous Operation
Setting SEL = high and SEL = low enables the four channels to operate independently as LVECL-toLVPECL translators. The CLK signal is ignored in this mode. In asynchronous mode, the CLK signal should be set to either logic low or high state to minimize noise coupling.
Synchronous Operation
Setting SEL = low and SEL = high enables all four channels to operate in synchronized mode. In this mode, buffered inputs are clocked into flip-flops simultaneously on the rising edge of the differential clock input (CLK and CLK).
Supply Voltages
For interfacing to differential LVECL input levels, the VEE range is -2.0V to -3.6V with GND = 0. The VCC range is from 2.375V to 3.6V, compatible with LVPECL logic. Output levels are referenced to VCC.
Data Inputs
The MAX9420/MAX9421 have open inputs and require external termination. The MAX9422/MAX9423 have integrated 100 differential input termination resistors from IN_ to IN_, reducing external component count.
Differential Signal Input Limit
The maximum signal magnitude of all the differential inputs is 3.0V.
GND VID VID = 0
VIHD (MAX)
VCC
VILD (MAX) VOH - VOL VIHD (MIN) VID VEE INPUT VOLTAGE DEFINITION VID = 0 VILD (MIN) OUTPUT VOLTAGE DEFINITION VOCM
VOH
VOL
GND
Figure 1. Input and Output Voltage Definitions 6 _______________________________________________________________________________________
Quad Differential LVECL-to-LVPECL Translators MAX9420-MAX9423
IN_ IN_ 100k IN_ IN_
MAX9420/MAX9421
MAX9422/MAX9423
VCC VCC ROUT OUT_ OUT_ OUT_ ISINK ISINK VEE ROUT OUT_
MAX9420/MAX9422
MAX9421/MAX9423 Figure 2. Input and Output Configurations
IN_ VIHD - VILD IN_
tPLH1 OUT_ VOH - VOL OUT_
tPHL1
80%
VOH - VOL
80%
OUT_ - OUT_
DIFFERENTIAL OUTPUT WAVEFORM
20%
VOH - VOL
20%
tR
tF SEL = HIGH EN = HIGH
Figure 3. IN-to-OUT Propagation Delay Timing Diagram
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7
Quad Differential LVECL-to-LVPECL Translators MAX9420-MAX9423
CLK VIHD - VILD CLK
tH IN_
tS
tH
VIHD - VILD IN_
tPLH2 OUT_ VOH - VOL OUT_
tPHL2
SEL = LOW EN = HIGH
Figure 4. CLK-to-OUT Propagation Delay Timing Diagram
Applications Information
Input Bias
Unused inputs should be biased or driven as shown in Figure 5. This avoids noise coupling that might cause toggling at the unused outputs.
ple parallel vias for ground-plane connection to minimize inductance.
Circuit Board Traces
Input and output trace characteristics affect the performance of the MAX9420-MAX9423. Connect each of the inputs and outputs to a 50 characteristic impedance trace. Avoid discontinuities in differential impedance and maximize common-mode noise immunity by maintaining the distance between differential traces and avoid sharp corners. Minimize the number of vias to prevent impedance discontinuities. Reduce the reflections by maintaining 50 characteristic impedance through connectors and across cables. Minimize skew by matching the electrical length of the traces.
Output Termination
Terminate open-emitter outputs (MAX9420/MAX9422) through 50 to VCC - 2V or use an equivalent Thevenin termination. Terminate outputs using identical termination on each for the lowest output-to-output skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if OUT_ is used as a single-ended output, terminate both OUT_ and OUT_. Ensure that the output currents do not exceed the current limits as specified in the Absolute Maximum Ratings table. Under all operating conditions, the device's total thermal limits should be observed.
Chip Information
TRANSISTOR COUNT: 927 PROCESS: Bipolar
Power-Supply Bypassing
Adequate power-supply bypassing is necessary to maximize the performance and noise immunity. Bypass VCC to GND and VEE to GND with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the 0.01F capacitor closest to the device pins. Use multi-
8
_______________________________________________________________________________________
Quad Differential LVECL-to-LVPECL Translators MAX9420-MAX9423
GND VCC VCC
IN_ OUT_ 100 OUT_ IN_ 1k 1/4
IN_ OUT_ 100 OUT_ IN_
MAX9420 MAX9421
1k
1/4
MAX9422 MAX9423
VEE
VEE
Figure 5. Input Bias Circuits for Unused Inputs
Pin Configurations (continued)
OUT0 OUT0 GND VCC
TOP VIEW
IN0 IN0 32 31
IN1
30
29
28
27
26
25
*
IN1
*
VEE SEL SEL CLK CLK EN EN VEE
1 2 3 4 5 6 7 8
24 23 22
VCC OUT1 OUT1 GND GND OUT2 OUT2 VCC
MAX9420 MAX9421 MAX9422 MAX9423
21 20 19 18 17
10
11
12
13
14
15
*
IN3
16
9
*
IN3
OUT3
OUT3
QFN-EP*
*EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO VEE LEAD UNDER PACKAGE.
_______________________________________________________________________________________
GND
VCC
IN2
IN2
9
Quad Differential LVECL-to-LVPECL Translators MAX9420-MAX9423
Functional Diagram
IN0 IN0 D D CK CK Q Q 1
0
OUT0 OUT0
IN1 IN1 D D CK CK Q Q
1
0
OUT1 OUT1
IN2 IN2 D D CK CK Q Q
1
0
OUT2 OUT2
IN3 IN3 D D CK CK Q Q
1
0
OUT3 OUT3
CLK CLK
SEL SEL
EN EN
10
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Quad Differential LVECL-to-LVPECL Translators
Package Information
32L TQFP, 5x5x01.0.EPS
MAX9420-MAX9423
______________________________________________________________________________________
11
Quad Differential LVECL-to-LVPECL Translators MAX9420-MAX9423
Package Information (continued)
12
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Quad Differential LVECL-to-LVPECL Translators
Package Information (continued)
MAX9420-MAX9423
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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